Fin and Gate-All-Around Transistors (FinFET / GAA)

As channel length shrinks, a planar (single-gate) structure's gate can no longer control the channel potential well enough — source and drain begin directly "interfering" with the channel (short-channel effects). Additional gates (2-3 for FinFET, 4 for GAA) restore control, allowing channel length to continue shrinking.

$\lambda=\sqrt{\varepsilon_{si}t_{si}t_{ox}/(n\varepsilon_{ox})}$ — the more gates ($n$) or the thinner the body ($t_{si}$), the smaller $\lambda$, and the shorter the channel length that can operate reliably (rule of thumb: $L\gtrsim6\lambda$).

By stacking several nanosheets on top of each other (e.g. 3 sheets), the total effective width multiplies with the stack count, while the horizontal chip area (footprint) stays the same — this directly increases current per unit area, critical for densely integrated circuits.

DIBL (Drain-Induced Barrier Lowering) describes how a high drain voltage "helps" lower the channel's potential barrier, artificially reducing the threshold voltage and increasing off-state current. Multi-gate architectures significantly reduce DIBL, since the gates "shield" the channel from the drain's field.